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copyright ? anpec electronics corp. rev. a.2 -apr., 2004 APA2030/2031 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. stereo 2.6w audio amplifier(with gain control) features general description applications ? ? ? ? ? low operating current with 6ma ? ? ? ? ? improved depop circuitry to eliminate turn-on transients in outputs ? ? ? ? ? high psrr ? ? ? ? ? internal gain control, eliminate external components. ? ? ? ? ? 2.6w per channel output power into 3 ? load at 5v, btl mode ? ? ? ? ? multiple input modes allowable selected by hp /line pin (APA2030) ? ? ? ? ? two output modes allowable with btl and se modes selected by se/btl pin (for APA2030 only) ? ? ? ? ? low current consumption in shutdown mode (50 a) ? ? ? ? ? short circuit protection ? ? ? ? ? tssop-24-p (APA2030) and tssop-20-p (apa2031) with thermal pad package. ? ? ? ? ? notebook pc ? ? ? ? ? lcd monitor APA2030/1 is a monolithic integrated circuit, which provides internal gain control, and a stereo bridged audio power amplifiers capable of producing 2.6w (1.9w) into 3 ? with less than 10% (1.0%) thd+n. by control the two gain setting pins, gain0 and gain1, the amplifier can provide 6db, 10db, 15.6db, and 21.6db gain settings. the advantage of internal gain setting can be less components and pcb area. both of the depop circuitry and the thermal shutdown pro- tection circuitry are integrated in APA2030/1, that reduces pops and clicks noise during power up or shutdown mode operation. it also improved the power off pop noise and protects the chip from being de- stroyed by over temperature and short current failure. to simplify the audio system design APA2030 com- bines a stereo bridge-tied loads (btl) mode for speaker drive and a stereo single-end (se) mode for headphone drive into a single chip, where both modes are easily switched by the se/btl input control pin signal. besides the multiple input selections is used for portable audio system. apa2031 eliminates both input selection and single-end (se) mode function to simplifying the design and save the pcb space. APA2030/1 handling code temp. range package code package code r : tssop-p * temp. range i : - 40 to 85 c handling code tu : tube tr : tape & reel ty : tray lead free code l : lead free device blank : original device APA2030/1 r : APA2030/1 xxxxx xxxxx - date code lead free code ordering and marking information
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 2 block diagram pin assignment APA2030 lout+ 4 lout- 9 21 rout+ 16 rout- rin+ 8 lin+ 10 bypass 11 llinein 5 23 rlinein lhpin 6 20 rhpin ga in0 2 15 se/btl 22 shutdown ga in1 3 24 gnd 13 gnd 19 v dd 18 pv dd pv dd 7 gnd 1 gnd 12 1 4 pcb eep 17 hp/line top view (APA2030) a p a 2030_p ino ut lout+ 4 lin+ 9 17 rin- 12 nc lout- 8 by pa ss 10 lin- 5 19 shutdown pv dd 6 16 v dd ga in0 2 11 gnd 18 rout+ ga in1 3 20 gnd 15 pv dd 14 rout- rin+ 7 gnd 1 13 gnd top view (apa2031) shutdown ckt h p/l in e mux mux se/b tl lout+ lout- rout+ rout- llinein rlinein lhpin rhpin hp/line se/btl shutdow n by pa ss pc -b eep ckt pcb eep vbias gain selectable vbias lin+ rin+ gia n1 ga in0 a p a 2030_b lock
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 3 parameter rating supply voltage range, v dd , pv dd -0.3v to 6v input voltage range at se/btl, hp/line, shutdown, -0.3v to v dd operating ambient temperature range, t a -40c to 85c maximum junction temperature, t j internal limited storage temperature range, t stg -65c to 150c soldering temperature, 10 seconds, t s 260c electrostatic discharge, v esd -3000 to 3000*1 -200 to 200*2 power dissipation, p d internal limited block diagram apa2031 absolute maximum ratings (over operating free-air temperature range unless otherwise noted.) note: *1. human body model: c=100pf, r=1500 ? , 3 positives pulse plus 3 negative pulses *2. machine model: c=200pf, l=0.5mh, 3 positive pulses plus 3 negative pulses shutdown ckt lout+ lout- rout+ rout- shutdown bypass vbias gain selectable vbias lin+ rin+ lin- ga in0 ga in1 rin- apa2031_block
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 4 recommended operating conditions thermal characteristics symbol parameter value unit r thja thermal resistance from junction to ambient in free air tssop-p24* tssop-p20* 45 48 c/w electrical characteristics (v dd =5v,-20c copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 5 symbol parameter test condition min. typ. max. unit thd=10%, fin=1khz, rl=32 ? 110 mw p o maximum output power thd=1%, fin=1khz, rl=32 ? 90 mw thd+n total harmonic distortion plus noise po=75mw, rl=32 ? .fin=1khz 0.03 % psrr power ripple rejection ratio vin=0.2vrms, rl=32 ? , cb=0.47 f, f=120, 55 db se/btl attenuation 80 db xtalk channel separation f=1khz, cb=0.47 f, 65 db hp/line input separation f=1khz, cb=0.47 f, btl 80 db s/n signal to noise ratio po=75mw, rl=32 ? , a_weight, 100 db symbol parameter test condition min. typ. max. unit thd=10%, f in =1khz, rl=3 ? 2.6 w thd=10%, f in =1khz, rl=4 ? 2.3 w thd=10%, f in =1khz, rl= 8? 1.5 w thd=1%, f in =1khz, rl=3 ? 1.9 w thd=1%, f in =1khz, rl=4 ? 1.7 w p o maximum output power thd=1%, f in =1khz, rl=8 ? 1 1.1 w po=1.1w, rl=4 ? fin=1khz 0.05 % thd+n total harmonic distortion plus noise po=0.7w, rl=8 ? , fin=1khz 0.04 % psrr power ripple rejection ratio vin=0.2vrms, rl=8 ? , cb=0.47 f, f=120hz 85 db xtalk channel separation f=1khz, cb=0.47 f, 95 db hp/line input separation f=1khz, cb=0.47 f, 80 db s/n signal to noise ratio po=1.1w, rl=8 ? , a_weight 105 db electical characteristics (cont.) operating characteristics, btl mode vdd=5v, t a =25c, rl=4 ? ? ? ? ? , gain=6db, (unless otherwise noted) operating characteristics, se mode ( for APA2030 only) vdd=5v, t a =25c, rl=32 ? ? ? ? ? , gain=4, 1db, (unless otherwise noted)
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 6 pin name pin no. config. function description gnd 1, 12, 13, 24 - ground connection, connected to thermal pad. gain0 2 i/p input signal for internal gain setting gain1 3 i/p input signal for internal gain setting lout+ 4 o/p left channel positive output in btl mode and se mode llinein 5 i/p left channel line input terminal, selected when hp/line is held low. rlinein 23 i/p right channel line input terminal, selected when hp/line is held low. lhpin 6 o/p left channel headphone input terminal, selected when hp/line is held high. pv dd 7, 18 - supply voltage only for power amplifier rin+ 8 i/p right channel positive signal input, when differential signal is accepted. lout- 9 o/p left channel negative output in btl mode and high impedance in se mode lin+ 10 i/p left channel positive signal input, when differential signal is accepted. bypass 11 - bypass voltage pcbeep 14 i/p pc-beep signal input se/btl 15 i/p output mode control input pin, high for se output mode and low for btl mode rout- 16 o/p right channel negative output in btl mode and high impedance in se mode hp/line 17 i/p multi-input selection input, headphone mode when held high, line-in mode when held low v dd 19 - supply voltage for internal circuit excepting power amplifier. rhpin 20 i/p right channel headphone input terminal, selected when hp/line is held high. rout+ 21 o/p right channel positive output in btl mode and se mode shutdown 22 i/p it will be into shutdown m ode w hen pull low rlinein 23 i/p right channel line input terminal, selected when hp/line is held low pin descriptions APA2030 apa2031 pin name pin no. config. function description gnd 1, 11, 13, 20 - ground connection, connected to thermal pad. gain0 2 i/p input signal for internal gain setting gain1 3 i/p input signal for internal gain setting lout+ 4 o/p left channel positive output lin- 5 i/p left channel negative audio signal input pv dd 6,15 - supply voltage only for power amplifier rin+ 7 i/p right channel positive audio signal input lout- 8 o/p left channel negative output lin+ 9 i/p left channel positive audio signal input bypass 10 - bypass voltage nc 12 - no connection rout- 14 o/p right channel negative output v dd 16 - supply voltage for internal circuit excepting power amplifier
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 7 pin name pin no. config. function description rin+ 17 i/p right channel negative audio signal input rout+ 18 o/p right channel positive output shutdown 19 i/p it will be into shutdown mode when pull low pin description hp/ line se/btl shutdown pcbeep operating mode x x l disable shutdown mode l l h disable line input, btl out h l h disable hp input, btl out l h h disable line input, se out h h h disable hp input, se out x x x enable pcbeep input, btl out control input table ( for APA2030 only) apa2031 gain0 gain1 ri rf av 0 0 90k ? 90k ? 6db 0 1 69k ? 111k ? 10db 1 0 42k ? 138k ? 15.6db 1 1 25.7k ? 154.3k ? 21.6db gain setting table (for both APA2030 and apa2031)
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 8 typical application circuit apa 2030 (f (for APA2030 using se input signal) 4 ? 4 ? ri ng headphone jack sleeve control pin tip se/btl signal 0.47 f 0.47 f 220 f 220 f 1k ? 1k ? r-line r-hp vdd 100k ? shutdown signal shutdown ckt hp/line mux mux se/btl lout+ lout- rout+ rout- llinein rlinein lhpin rhpin hp/line se/btl bypass pc-beep ckt pcbeep vbias gai n selectable vbias lin+ rin+ 0.47 f beep signal 0.47 f 0.47 f l-line l-hp 0.47 f vdd v dd pv dd gnd 0 ? 0.47 f 0.47 f gain0 gain1 100 f 0.1 f APA2030appckt shutdown hp/line control signal 100k ? se/btl signal
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 9 4 ? 4 ? shutdown signal shutdown ckt lout+ lout- rout + rout - lin- rin- shutdown bypass vbias gain selectable vbias lin+ rin+ l-input 0.47 f vdd vdd pvdd gnd 0 ? 0.47 f gain0 gain1 0.47 f 0.47 f 0.47 f r-input 100 f 0.1 f apa 2031 typical application circuit (for apa2031 using se input signal)
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 10 0.01 10 0.1 1 0 3 0.5 11.52 2.5 0.01 10 0.1 1 10m 5 100m 1 2 0.01 10 0.1 1 10m 5 100m 1 0.01 10 0.1 1 0250 50 100 150 200 typical characteristics thd+n vs. output power thd+n vs. output power thd+n (%) output power (w) output power (mw) thd+n (%) r l =3 ? v dd =5v a v =6db f=1khz btl r l =8 ? r l =4 ? v dd =5v a v =4.1db f=1khz c out =330 f se r l =32 ? r l =16 ? output power (w) output power (w) thd+n vs. output power thd+n vs. output power thd+n (%) thd+n (%) f=15khz f=1khz f=30hz v dd =5v a v =6db r l =3 ? btl f=15khz f=1khz f=30hz v dd =5v a v =15.6db r l =3 ? btl
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 11 0.01 10 0.1 1 10m 5 100m 1 2 0.01 10 0.1 1 10m 5 100m 1 2 0.0 1 10 0.1 1 10m 5 100m 1 2 typical characteristics (cont.) 0.01 10 0.1 1 10m 5 100m 1 2 thd+n vs. output power thd+n vs. output power output power (w) output power (w) thd+n (%) thd+n (%) f=15khz f=1khz f=30hz v dd =5v a v =6db r l =4 ? btl f=15khz f=1khz f=30hz v dd =5v a v =15.6db r l =4 ? btl thd+n vs. output power output power (w) thd+n (%) output power (w) v dd =5v a v =6db r l =8 ? btl f=15khz f=1khz f=30hz thd+n (%) thd+n vs. frequency v dd =5v a v =15.6db r l =8 ? btl f=15khz f=1khz f=30hz
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 12 0.01 10 0.1 1 20 20k 100 1k 10k 0.01 10 0.1 1 20 20k 100 1k 10k typical characteristics (cont.) 0.01 10 0.1 1 10m 300m 50m 100m 200m 0.01 10 0.1 1 10m 300m 50m 100m 200m thd+n vs. output power thd+n vs. output power thd+n (%) thd+n (%) output power (w) output power (w) f=15khz f=1khz f=30hz f=15khz f=1khz f=30hz v dd =5v a v =4db r l =16 ? c out =1000 f se v dd =5v a v =4.1db r l =32 ? c out =1000 f se thd+n vs. frequency frequency (hz) frequency (hz) thd+n vs. frequency thd+n (%) thd+n (%) p o =1.75w a v =6db v dd =5v p o =1.75w r l =3 ? btl v dd =5v a v =6db r l =3 ? btl p o =1w a v =15.6db
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 13 0.01 10 0.1 1 20 20k 100 1k 10k 0.01 10 0.1 1 20 20k 100 1k 10k 0.01 10 0.1 1 20 20k 100 1k 10k typical characteristics (cont.) 0.01 10 0.1 1 20 20k 100 1k 10k thd+n vs. frequency thd+n vs. frequency thd+n (%) thd+n (%) frequency (hz) frequency (hz) p o =1.5w p o =0.75w a v =6db a v =15.6db v dd =5v a v =6db r l =4 ? btl v dd =5v p o =1.5w r l =4 ? btl frequency (hz) frequency (hz) thd+n (%) thd+n (%) thd+n vs. frequency thd+n vs. frequency p o =1w p o =0.5w a v =6db a v =15.6db v dd =5v a v =6db r l =8 ? btl v dd =5v p o =1w r l =8 ? btl
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 14 +120 +240 +130 +140 +150 +160 +170 +180 +190 +200 +210 +220 +230 -10 +6 -8 -6 -4 -2 -0 +2 +4 10 200k 100 1k 10k 100k +120 +270 +130 +140 +150 +160 +170 +180 +190 +200 +210 +220 +230 +240 +250 +260 -0 +20 +2 +4 +6 +8 +10 +12 +14 +16 +18 10 200k 100 1k 10k 100k 0.01 10 0.1 1 20 20k 100 1k 10k 0.01 10 0.1 1 20 20k 100 1k 10k typical characteristics (cont.) thd+n vs. frequency thd+n vs. frequency thd+n (%) thd+n (%) frequency (hz) frequency (hz) p o =75mw p o =150mw p o =75mw p o =25mw v dd =5v a v =4.1db r l =16 ? c out =1000 f se v dd =5v a v =4.1db r l =32 ? c out =1000 f se frequency response frequency response frequency (hz) frequency (hz) gain (db) phase (degress) phase (degress) gain (db) gain phase gain phase v dd =5v r l =4 ? a v =6db p o =1w btl v dd =5v r l =4 ? a v =15.6db p o =1w btl
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 15 +100 +300 +120 +140 +160 +180 +200 +220 +240 +260 +280 -5 +5 -4 -3 -2 -1 +0 +1 +2 +3 +4 10 200k 100 1k 10k 100k -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k 100 1k 10k +120 +270 +130 +140 +150 +160 +170 +180 +190 +200 +210 +220 +230 +240 +250 +260 -0 +10 +1 +2 +3 +4 +5 +6 +7 +8 +9 10 200k 100 1k 10k 100k -140 +0 -120 -100 -80 -60 -40 -20 20 20k 100 1k 10k typical characteristics (cont.) frequency response frequency response frequency (hz) frequency (hz) gain (db) gain (db) phase (degress) phase (degress) gain phase v dd =5v r l =8 ? a v =10db p o =0.5w btl gain phase v dd =5v r l =32 ? a v =4.1db v in =1v se crosstalk vs. frequency crosstalk vs. frequency crosstalk (db) crosstalk (db) frequency (hz) frequency (hz) v dd =5v r l =4 ? a v =6db p o =1.5w se v dd =5v r l =32 ? a v =4.1db v in =1v c out =330 f se left to right right to left left to right right to left
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 16 -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k 100 1k 10k 1 100 2 5 10 20 50 20 20k 100 1k 10k 1 100 2 5 10 20 50 20 20k 100 1k 10k -100 +0 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k 100 1k 10k typical characteristics (cont.) psrr vs. frequency psrr vs. frequency psrr (db) psrr (db) frequency (hz) frequency (hz) v dd =5v r l =4 ? c b =0.47 f btl v dd =5v r l =32 ? c b =0.47 f se output noise voltage vs. frequency output noise voltage vs. frequency frequency (hz) frequency (hz) output noise voltage ( v) output noise voltage ( v) v dd =5v r l =32 ? a v =4.1db se filter bw < 22khz a-weight filter bw < 22khz a-weight v dd =5v r l =4 ? a v =6db btl
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 17 0 20 40 60 80 100 120 140 160 180 200 0 50 100 150 200 250 300 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.5 1.0 1.5 2.0 2.5 0 1 2 3 4 5 6 7 3.0 3.5 4.0 4.5 5.0 5.5 6.0 typical characteristics (cont.) supply current vs. supply voltage supply voltage (v) supply current (ma) power dissipation vs. output power power dissipation (w) output power (w) output power (mw) power dissipation (mw) power dissipation vs. output power no load btl se v dd =5v btl r l =3 ? r l =4 ? r l =8 ? v dd =5v se r l =8 ? r l =16 ? r l =32 ?
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 18 application descriptions btl operation the APA2030/1 has two pairs of operational amplifi- ers internally, allowed for different amplifier configurations. figure 1: APA2030 internal configuration (each channel) the op1 and op2 are all differential drive configuration, the differential drive configuration dou- bling the voltage swing on the load compare to the single-ending configuration, the differential gain for each channel is 2 x (gain of se mode). by driving the load differentially through outputs out+ and out-, an amplifier configuration commonly re- ferred to as bridged mode is established. btl mode operation is different from the classical single-ended se amplifier configuration where one side of its load is connected to ground. a btl amplifier design has a few distinct advantages over the se configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. four times the output power is possible as compared to a se amplifier under the same conditions. a btl configuration, such as the one used in APA2030/1, also creates a second ad- vantage over se amplifiers. since the differential outputs, rout+, rout-, lout+, and lout-, are bi- ased at half-supply, no need dc voltage exists across the load. this eliminates the need for an output cou- pling capacitor which is required in a single supply, se configuration. single-ended operation (for APA2030 only) consider the single-supply se configuration shown application circuit. a coupling capacitor is required to block the dc offset voltage from reaching the load. these capacitors can be quite large (approximately 33 f to 1000 f) so they tend to be expensive, oc- cupy valuable pcb area, and have the additional drawback of limiting low-frequency performance of the system (refer to the output coupling capacitor). the rules described should be following relationship: ? 125k cbypass 1 i i c r 1 << c l c r 1 (1) output se/btl operation (for APA2030 only) the ability of the APA2030 to easily switch between btl and se modes is one of its most important costs saving features. this feature eliminates the require- ment for an additional headphone amplifier in appli- cations where internal stereo speakers are driven in btl mode but external headphone or speakers must be accommodated. internal to the APA2030, two separate amplifiers drive out+ and out- (see figure 1). the se/btl input controls the operation of the follower amplifier that drives lout- and rout-. ? ? ? ? ? when se/btl is held low, the op2 is actived and the APA2030 is in the btl mode. ? ? ? ? ? when se/btl is held high, the op2 is in a high output impedance state, which configures the APA2030 as se driver from out+. i dd is re- duced by approximately one-half in se mode. control of the se/btl input can be a logic-level ttl source or a resistor divider network or the stereo head- phone jack with switch pin as shown in application circuit. v bias op1 op2 in pu t- - + - + in pu t+ out+ out- d i f f _a m p _c o n f i g
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 19 ? ? ? ? ? to select the line inputs, set hp/line pin tied to low level ? ? ? ? ? to enable the headphone inputs, set hp/ line pin tied to high level refer to the application circuit, the voltage divider of 100k ? and 1k ? sets the voltage at the hp/line pin to be approximately 50mv when there are no head- phones plugged into the system. this logic low volt- age at the hp/line pin enables the APA2030 and places it line input mode operation. differential input operation APA2030/1 can accepted the differential input signal, and it?s can improve the cmrr (common mode re- jection ratio). for example: when apply differential in- put signals to apa2031, connect positive input sig- nals to the in+ (lin+ and rin+) of apa2031 and nega- tive input signals to the in- (lin- and rin-) of apa2031. when input signals are single-end, just connect in+ (lin+ and rin+) to ground via a capacitor. input resistance, ri the APA2030/1 provides four gain setting decided by gain0 and gain1 input ins in differential mode and it become 4.1db fixed gain when se mode is selected (for APA2030). in table 1,internal resistors ri and rf according to btl operation set the gain for each au- dio input of the APA2030/1. figure 2: se/btl input selection by phonejack plug in figure 2, input se/btl operates as follows: when the phonejack plug is inserted, the 1k ? resis- tor is disconnected and the se/btl input is pulled high and enables the se mode. when the input goes high level, the out- amplifier is shutdown causing the speaker to mute. the out+ amplifier then drives through the output capacitor (c o ) into the headphone jack. when there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by re- sistors 100k ? and 1k ? . resistor 1k ? then pulls low the se/btl pin, enabling the btl function. input hp/line operation (for APA2030 only) APA2030 amplifier has two separate inputs for each of the left and right stereo channels. an internal multi- plexer selects which input will be connected to the amplifier based on the state of the hp/line pin on the ic. when a set of headphones is plugged into the system, the contact pin of the headphone jack is disconnected from the signal pin, interrupting the voltage divider set up by resistors 100k ? . resistor 100k ? then pulls-up gain0 gain1 ri rf se/btl av 0 0 90k ? 90k ? 0 6db 0 1 69k ? 111k ? 0 10db 1 0 42k ? 138k ? 0 15.6db 1 1 25.7k ? 154.3k ? 0 21.6db x x 69k ? 111k ? 1 4.1db btl mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. the input resis- tance has wide variation (+/-10%) caused by manufacture. i nput capacitor, ci in the typical application an input capacitor, ci, is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. in this case, ci and the minimum input impedance ri form a high-pass filter with the corner frequency determined in the follow equation: application descriptions table 1: the close loop gain setting resistance ri/rf the hp/line pin, enabling the headphone input function. ring 1k ? headphone jack sleeve control pin tip vdd 100k ? se/btl se /bt l _ s w i tc h 100k ?
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 20 the value of ci is important to consider as it directly affects the low frequency performance of the circuit. consider the example where ri is 90k ? when 6db gain is setting and the specification calls for a flat bass response down to 40hz . equation is reconfigured as follow: ci= (3) consider to input resistance variation, the ci is 0.04 f so one would likely choose a value in the range of 0.1 f to 1.0 f. a further consideration for this capacitor is the leak- age path from the input source through the input net- work (ri+rf, ci) to the load. this leakage current creates a dc offset voltage at the input to the ampli- fier that reduces useful headroom, especially in high gain applications. for this reason a low-leakage tan- talum or ceramic capacitor is the best choice. when polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at v dd /2, which is likely higher that the source dc level. please note that it is important to confirm the capacitor po- larity in the application. effective bypass capacitor, cbypass as with any power amplifier, proper supply bypass- ing is critical for low noise performance and high power supply rejection. the capacitor location on both the bypass and power supply pins should be as close to the device as possible. the effect of a larger half supply bypass capacitor is improved psrr due to increased half- supply stability. typical applications employ a 5v regu- lator with 1.0 f and a 0.1 f bypass capacitors which aid in supply filtering. this does not eliminate the need for bypassing the supply nodes of the APA2030/1. the selection of bypass capacitors, especially cb, is thus dependent upon desired psrr requirements, click and pop performance. the capacitor is fed from a 125k ? source inside the amplifier. bypass capacitor, cb, values of 3.3 f to 10 f ceramic or tantalum low-esr capacitors are recommended for the best thd and noise performance. the bypass capacitance also effect to the start up time. it is determined in the follow equation: tstart up =5x(cbypassx125k ? ) (5) output coupling capacitor, cc (for APA2030 only) in the typical single-supply se configuration, an out- put coupling capacitor (cc) is required to block the dc bias at the output of the amplifier thus preventing dc currents in the load. as with the input coupling capacitor, the output coupling capacitor and imped- ance of the load form a high-pass filter governed by equation. fc(highpass)= c l c r 2 1 (6) for example, a 330 f capacitor with an 8 ? speaker would attenuate low frequencies below 60.6hz. the main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. large values of c c are required to pass low frequencies into the load. power supply decoupling, cs application descriptions rifc 2 1 125k cbypass 1 << (4) the APA2030/1 is a high-performance cmos audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distor- tion (thd) is as low as possible. to avoid start-up pop noise occurred, the bypass volt- age should be rise slower then the input bias voltage and the relationship shown in equation should be maintained. f c (highpass)= (2) ci rimin 2 1 180k ci 1
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 21 power supply decoupling also prevents the oscilla- tions causing by long lead length between the ampli- fier and the speaker. the optimum decoupling is achieved by using two dif- ferent type capacitors that target on different type of noise on the power supply leads. for higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance(esr) ceramic capacitor, typically 0.1 f placed as close as possible to the device v dd lead works best. for filtering lower- frequency noise signals, a large aluminum electrolytic capacitor of 10 f or greater placed near the audio power amplifier is recommended. shutdown function in order to reduce power consumption while not in use, the APA2030/1 contains a shutdown pin to externally turn off the amplifier bias circuitry. this shutdown fea- ture turns the amplifier off when a logic low is placed on the shutdown pin. the trigger point between a logic high and logic low level is typically 2.0v. it is best to switch between ground and the supply v dd to provide maximum device performance. by switching the shutdown pin to low, the amplifier enters a low-current state, i dd <50 a. APA2030 is in shutdown mode, except pc-beep detect circuit. on normal operating, shutdown pin pull to high level to keeping the ic out of the shutdown mode. the shut- down pin should be tied to a definite voltage to avoid unwanted state changes. pc-beep detection ( for APA2030 only) APA2030 integrates a pcbeep detect circuit for notebook pc used. when pc-beep signal drive to pcbeep input pin, and pcbeep mode is active. APA2030 will force to btl mode and the internal gain fixed as -10db. the pcbeep signal becomes the amplifier input signal and play on the speaker without coupling capacitor. if the amplifier in the shutdown mode, it will out of shutdown mode whenever pcbeep mode enable. the APA2030 will return to previous setting when it is out of pc-beep mode. the input impedance is 100k ? on pcbeep input pin. optimizing depop circuitry circuitry has been included in the APA2030/1 to mini- mize the amount of popping noise at power-up and when coming out of shutdown mode. popping occurs whenever a voltage step is applied to the speaker. in order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. the value of ci will also affect turn-on pops. (refer to effective bypass capacitance) the bypass voltage rise up should be slower than input bias voltage. although the bypass pin current source cannot be modified, the size of cb can be changed to alter the device turn-on time and the amount of clicks and pops. by increasing the value of cb, turn-on pop can be reduced. however, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. there is a linear relationship between the size of cb and the turn-on time. in a se(for APA2030) configuration, the output cou- pling capacitor, c c , is of particular concern. this ca- pacitor discharges through the internal 10k ? resistors. depending on the size of c c , the time constant can be relatively large. to reduce transients in se mode, an external 1k ? resistor can be placed in parallel with the internal 10k ? resistor. the tradeoff for using this resistor is an increase in quiescent current. in the most cases, choosing a small value of ci in the range of 0.33 f to 1 f, cb being equal to 0.47 f and an external 1k ? resistor should be placed in parallel with the internal 10k ? resistor should produce a virtu- ally clickless and popless turn-on. a high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. so it is advantageous to use low-gain configurations. btl amplifier efficiency an easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. the follow- ing equations are the basis for calculating amplifier efficiency. application descriptions
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 22 efficiency = (7) where: p o = = v o rms = (8) psup = v dd * i dd avg = l p r 2v efficiency of a btl configuration: sup o p p = ( l p p 2r v v ) / (v dd x l p r 2v ) = dd p 4v v (10) table 2 calculates efficiencies for four different output power levels. note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. note that the internal dissipation at full output power is less than in the half power range. calculating the efficiency for a specific system is the key to proper power supply design. for a stereo 1w audio system with 8 ? loads and a 5v supply, the maximum draw on the power supply is almost 3w. po (w) efficiency (%) i dd (a) v pp (v) p d (w) 0.25 31.25 0.16 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 **high peak voltages cause the thd to increase. table 2. efficiency vs output power in 5v/8 ? btl systems a final point to remember about linear amplifiers (either se or btl) is how to manipulate the terms in the effi- ciency equation to utmost advantage whenpossible. note that in equation, v dd is in the dominator. this indicates that as v dd goes down,efficiency goes up. in other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. power dissipation whether the power amplifier is operated in btl or se modes, power dissipation is a major concern. in equa- tion11 states the maximum power dissipation point for a se mode operating at a given supply voltage and driving a specified load. se mode : p d,max = l dd r 2 v (11) in btl mode operation, the output voltage swing is doubled as in se mode. thus the maximum power dissipation point for a btl mode operating at the same given conditions is 4 times as in se mode. btl mode : p d,max = (12) since the APA2030/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. even with this substantial increase in power dissipation, the APA2030/1 does not require extra heatsink. the power dissipation from equation12, assuming a 5v-power supply and an 8 ? load, must not be greater than the power dissipation that results from the equation13: p d,max = (13) for tssop-24 (APA2030) and tssop-20 (apa2031) package with and without thermal pad, the thermal resistance ( ja ) is equal to 45 o c/w and 48 o c/w, respectively. since the maximum junction temperature (t j,max ) of APA2030/1 is 150 o c and the ambient temperature (t a ) is defined by the power system design, the maximum application descriptions 2 2 ja a j.max t t ? sup o p p l o o r rms v rms v l p p 2r v v 2 v p l dd r 2 4v ? 2 2
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 23 thermal pad considerations the thermal pad must be connected to ground. the package with thermal pad of the APA2030/1 requires special attention on thermal design. if the thermal design issues are not properly addressed, the APA2030/1 4 ? will go into thermal shutdown when driving a 4 ? load. the thermal pad on the bottom of the APA2030/1 should be soldered down to a copper pad on the cir- cuit board. heat can be conducted away from the thermal pad through the copper plane to ambient. if the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the ther- mal pad to the bottom plane. for good thermal conduction, the vias must be plated through and sol- der filled. the copper plane used to conduct heat away from the thermal pad should be as large as practical. if the ambient temperature is higher than 25c, a larger copper plane or forced-air cooling will be re- quired to keep the APA2030/1 junction temperature below the thermal shutdown temperature (150c). in higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the ic out of thermal shutdown. application descriptions power dissipation which the ic package is able to handle can be obtained from equation13. once the power dissipation is greater than the maximum limit (p d,max ), either the supply voltage (v dd ) must bedecreased, the load impedance (r l ) must be in- creased or the ambient temperature should be reduced. thermal considerations linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. to calculate maximum ambient temperatures, first consideration is that the numbers from the power dissipation vs. output power graphs (page17) are per channel values, so the dissipation of the ic heat needs to be doubled for two-channel operation. given ja , the maximum allowable junction temperature (t j, max ), and the total internal dissipation (p d ), the maxi- mum ambient temperature can be calculated with the following equation. the maximum recommended junc- tion temperature for the APA2030/1 is 150c. the in- ternal dissipation figures are taken from the power dissipation vs. output power graphs. (page17) t a,max = t j,max - ? a p d (14) 150 - 45(0.8*2) = 78c (tssop-p24) 150 - 48(0.8*2) = 73.2c (tssop-p20) the APA2030/1 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150c to prevent damaging the ic.
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 24 packaging information tssop/ tssop-p ( reference jedec registration mo-153) millimeters inches dim min. max. min. max. a 1.2 0.047 a1 0.00 0.15 0.000 0.006 a2 0.80 1.05 0.031 0.041 d 6.4 (n=20pin) 7.7 (n=24pin) 9.6 (n=28pin) 6.6 (n=20pin) 7.9 (n=24pin) 9.8 (n=28pin) 0.252 (n=20pin) 0.303 (n=24pin) 0.378 (n=28pin) 0.260 (n=20pin) 0.311 (n=24pin) 0.386 (n=28pin) d1 4.2 bsc (n=20pin) 4.7 bsc (n=24pin) 3.8 bsc (n=28pin) 0.165 bsc (n=20pin) 0.188 bsc (n=24pin) 0.150 bsc (n=28pin) e 0.65 bsc 0.026 bsc e 6.40 bsc 0.252 bsc e1 4.30 4.50 0.169 0.177 e2 3.0 bsc (n=20pin) 3.2 bsc (n=24pin) 2.8 bsc (n=28pin) 0.118 bsc (n=20pin) 0.127 bsc (n=24pin) 0.110 bsc (n=28pin) l 0.45 0.75 0.018 0.030 l1 1.0 ref 0.039ref r 0.09 0.004 r1 0.09 0.004 s 0.2 0.008 8 0 8 ref 12 ref 3 12 ref 12 ref e2 bottom view (thermally enhanced variationds only) b d1 a1 a2 a d e 2 x e / 2 e1 e e/2 n 12 3 exposed thermal pad = one l (l1) (3) s (2) 0.25 gauge plane 1
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 25 terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb), 100%sn lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3. physical specifications reflow condition (ir/convection or vpr reflow) t 25 c to peak tp ramp-up t l ramp-down ts preheat tsmax tsmin t l t p 25 temperature time critical = one t l to t p classificatin reflow profiles sn-pb eutectic assembly pb-free assembly profile feature large body small body large body small body average ramp-up rate (t l to t p ) 3 c/second max. 3 c/second max. preheat temperature min (tsmin) temperature mix (tsmax) time (min to max)(ts) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds tsmax to t l - ramp-up rate 3 c/second max tsmax to t l temperature(t l ) time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(tp) 225 +0/-5 c 240 +0/-5 c 245 +0/-5 c 250 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 10-30 seconds 10-30 seconds 20-40 seconds ramp-down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note: all temperatures refer to topside of the package. measured on the body surface.
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 26 reliability test program carrier tape & reel dimensions a j b t2 t1 c t ao e w po p ko bo d1 d f p1 test item method description solderability mil-std-883d-2003 245 c, 5 sec holt mil-std-883d-1005.7 1000 hrs bias # 125 c pct jesd-22-b,a102 168 hrs, 100 % rh, 121 c tst mil-std-883d-1011.9 -65 c a 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm ! 2kv, vmm ! 200v latch-up jesd 78 10ms, 1 tr ! 100ma a pp lication a b c j t1 t2 w p e 330 1 100 ref 13 0.5 2 0.5 16.4 0.2 2 0.2 16 0.3 12 0.1 1.75 0.1 f d d1 po p1 ao bo ko t tssop- 24 7.5 0.1 1.5 +0.1 1.5 min 4.0 0.1 2.0 0.1 6.9 0.1 8.3 0.1 1.5 0.1 0.3 0.05 (mm)
copyright ? anpec electronics corp. rev. a.2 - apr., 2004 APA2030/2031 www.anpec.com.tw 27 application carrier width cover tape width devices per reel tssop- 24 16 21.3 2000 cover tape dimensions anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 customer service

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